执行以下程序段后，若输入时钟clk=50MHz，则clk_1Hz的频率是_____________。

module LED(clk,rst,led,dig,seg);
input clk,rst;
output reg[7:0] led;
output reg[7:0] dig;
output reg[7:0] seg;
reg[24:0] t;
reg clk_1hz;
reg[2:0] st;
//分频程序
always @(posedge clk)
begin
if(t == 5000000-1)
begin
t <= 0;
clk_1hz <= ~clk_1hz;
end
else
t <= t + 1;
end
always @(posedge clk_1hz)
begin
if(!rst)
st <= 0;
else
st <= st + 1;
case(st)
0:begin led <= 8'b11111110; dig <= 8'b11111110; seg <= 8'hf9; end
1:begin led <= 8'b11111101; dig <= 8'b11111101; seg <= 8'ha4; end
2:begin led <= 8'b11111011; dig <= 8'b11111011; seg <= 8'hb0; end
3:begin led <= 8'b11110111; dig <= 8'b11110111; seg <= 8'h99; end
4:begin led <= 8'b11101111; dig <= 8'b11101111; seg <= 8'h92; end
5:begin led <= 8'b11011111; dig <= 8'b11011111; seg <= 8'h82; end
6:begin led <= 8'b10111111; dig <= 8'b10111111; seg <= 8'hf8; end
7:begin led <= 8'b01111111; dig <= 8'b01111111; seg <= 8'h80; end
default:begin led <= 8'b11111111; dig <= 8'b11111111; seg <= 8'hff; end
endcase
end
endmodule



A.
1Hz B.
5Hz C.
10Hz D.
100Hz